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C8051F380/1/2/3/4/5/6/7/C
SFR Definition 17.1. VDM0CN: V DD Monitor Control
Bit
7
6
5
4
3
2
1
0
Name
VDMEN
VDDSTAT
Type
Reset
R/W
Varies
R
Varies
R
Varies
R
Varies
R
Varies
R
Varies
R
Varies
R
Varies
SFR Address = 0xFF; SFR Page = All Pages
Bit Name
Function
7
6
5:0
VDMEN
VDDSTAT
Unused
V DD Monitor Enable.
This bit turns the V DD monitor circuit on/off. The V DD Monitor cannot generate sys-
nition 17.2). Selecting the V DD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V DD Monitor and selecting it as a
reset source. See Table 5.4 for the minimum V DD Monitor turn-on time.
0: V DD Monitor Disabled.
1: V DD Monitor Enabled.
V DD Status.
This bit indicates the current power supply status (V DD Monitor output).
0: V DD is at or below the V DD monitor threshold.
1: V DD is above the V DD monitor threshold.
Read = 000000b; Write = Don’t care.
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD time-out, a reset will be generated. After a MCD reset,
the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads
0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of
the RST pin is unaffected by this reset.
17.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5). Com-
parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter
on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting
input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset
state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator0 as the
reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset.
132
Rev. 1.4
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